(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a memory cell a with capacitor over bitline, (COB), structure, dynamic random access memory, (DRAM), device, on a semiconductor substrate.
(2) Description of the Prior Art
To obtain maximum DRAM density, a capacitor over bitline, (COB), design, for high density DRAM chips has been used. The conventional approach of forming the COB structure, is to first form a bitline structure, followed by the formation of insulator spacers on the sidewall of the bitline structures. A self-aligned contact, (SAC), opening, is then made in a first insulator layer, through, (or between), the bitline structures, exposing an underlying conductive plug, which in turn overlays the source/drain region, used to communicate with a subsequent, overlying capacitor structure. However the stage in which the SAC is opened in a silicon oxide layer, after the formation of insulator spacers on the sides of the bitline structures, requires silicon nitride be used as the material for the sidewall spacers, due to the high etch rate ratio of silicon oxide to silicon nitride, needed for the SAC dry etching procedure. The use of silicon nitride sidewall spacers, featuring a higher dielectric constant than silicon oxide, results in unwanted increased capacitance, and decreased performance, for the DRAM cell.
This invention will describe a DRAM cell in which a SAC opening, to an underlying source/drain region, is made through bitline structures, but prior to the formation of insulator spacers on the sidewall of the bitline structures. Therefore this novel sequence allows silicon oxide spacers, to be formed on the sidewall of the bitline structures, thus resulting in decreased bitline to capacitor capacitance, when compared to counterparts fabricated using silicon nitride spacers. In addition since the spacers are formed after the SAC opening, possible damage to the insulator sidewall spacers, during the SAC opening, is avoided. This in turn allows the use of thinner insulator spacers, offering the attractive option of narrowing the SAC opening, increasing device density. Prior art, such as Tsai, in U.S. Pat. No. 5,763,306, show a COB DRAM device, however that prior art does not show the use of silicon oxide spacers, formed on the sides of bitline structures, after the creation of the SAC opening.